DEC PDP-11: Architecture, Models, Peripherals, and Unix Context

Digital Equipment Corporation's PDP-11 was a family of 16-bit minicomputers introduced in 1970 and developed through the 1970s and 1980s. It is important both as hardware and as an economic change in computing. A PDP-11 was not a “small mainframe” in every technical respect, nor a personal computer before its time. It was a comparatively affordable departmental machine: capable enough for laboratory control, engineering, transaction work, text processing, and multiuser timesharing, yet purchased and maintained by organizations that could not justify a large mainframe. Configurations mattered. A processor cabinet, memory, terminals, disks, tape drives, interfaces, and a service contract could cost dramatically more than the CPU module; no single PDP-11 configuration represents the whole family.

DEC, minicomputers, and a changing market

DEC had established a market for smaller interactive computers with earlier PDP systems. The PDP-11 combined a relatively regular instruction set with modular I/O and a broad range of prices. That range let a laboratory begin with a modest system and add memory, a disk, serial lines, or specialized interfaces as work demanded. It also encouraged an ecosystem of operating systems, instrument makers, communications products, and third-party boards. The practical attraction was often control of a local resource: a department could schedule its own machine, attach it to an experiment, and place terminals where users worked instead of submitting a batch job to a remote central computer.

“Minicomputer” described market position and physical scale more than one fixed architecture. A PDP-11 could fill racks, require air conditioning, and use moving-head disks; a later LSI-11 board could fit in a much smaller enclosure. Both differ from a mainframe in product positioning and from a microcomputer in integration and price, but those labels overlap historically. The family’s long life reflects component costs falling, semiconductor integration increasing, and customers protecting investments in software, interfaces, and trained operators.

Family chronology: related machines, not identical machines

Model or line	Period and implementation	Important qualification
PDP-11/20	1970, early UNIBUS model	A foundational low-end system; it lacks the later /45-style memory-management and separate instruction/data facilities.
PDP-11/35 and /40	Early/mid-1970s UNIBUS systems	Broader and faster configurations than the /20, but options and installed memory still determine capability.
PDP-11/45	1972 high-performance UNIBUS system	Its separate instruction/data-space memory-management capability was especially significant to time-sharing software; it is not a property of every PDP-11.
PDP-11/70	1975 high-end UNIBUS system	Added performance and larger physical-memory possibilities through its implementation; it remains a PDP-11, not a VAX.
LSI-11, 11/03, 11/23 and Q-bus successors	Mid-1970s onward, LSI processor boards and Q-bus systems	Usually much more compact. Compatibility is substantial but particular CPUs, MMUs, floating-point options, and bus features vary.

The /20 is often connected with early Unix because Bell Labs acquired one in 1970 and First Edition Unix ran on it. That historical fact does not make it a typical later Unix host: its limited addressing and memory facilities imposed severe limits. The /35 and /40 occupy useful middle ground in the product line, while the /45 and /70 are commonly associated with more capable multiuser and research installations. Later single-board LSI-11 designs brought PDP-11 programming and interfaces into embedded control and smaller systems. A model number alone is therefore not enough for an emulator configuration, a software installation, or a restoration plan; identify processor, memory-management option, bus, controller, and console hardware.

The common programming model

At its core, the PDP-11 is a 16-bit, byte-addressed, little-endian architecture. A 16-bit word occupies two consecutive byte addresses, with the low-order byte at the lower address. Registers R0 through R7 are 16-bit general registers. By convention and hardware definition, R6 is the stack pointer (SP) and R7 is the program counter (PC); code can use R0–R5 generally. The stack normally grows toward lower addresses. These conventions make procedure calls, interrupt entry, and compiler output compact, but software must still obey the calling convention chosen by its operating system or language runtime.

Feature	Family-wide architectural idea	Practical consequence
Registers	Eight 16-bit registers, with R6/SP and R7/PC roles.	Instructions can use registers uniformly and PC-relative code is natural.
Data order	Little-endian words in byte-addressed memory.	A word value `012345` has low byte `345` octal at the lower address; binary data needs explicit interpretation on another architecture.
Operands	Most instructions accept the same addressing-mode structure for source and destination.	Assembly is compact and expressive, though not every instruction or CPU option behaves identically.
Status	N, Z, V, and C condition codes in the processor status word.	Arithmetic and compare instructions feed conditional branches.
Control transfer	Traps, interrupts, and exceptions use vector locations and save machine state.	The OS can dispatch device and fault events; exact priority and optional features are implementation-sensitive.

The orthogonal addressing notation is a famous PDP-11 strength. Each operand specification combines a 3-bit mode and a 3-bit register. Register mode uses the register itself; register deferred uses the register as a pointer; autoincrement and autodecrement use a pointer while updating it; their deferred forms add an indirection; indexed and indexed-deferred forms add a displacement to a register. PC-relative addressing is indexed addressing with R7, so a program can reference nearby data without hard-coding its load address. The assembler's syntax varies slightly, but the underlying forms are recognizable: (R2)+ reads through R2 then increments it, and -(SP) decrements the stack pointer then uses the resulting address.

Using the PC with these modes gives conventional assembler shorthand its meaning. An immediate literal is fetched from the instruction stream, commonly written #value; an absolute address is commonly written @#address; a label or displacement can become PC-relative. Thus the same encoding framework supports constants, pointers, arrays, stack frames, and relocatable program text. Orthogonality reduces special cases for the programmer, but it does not mean all combinations have identical timing, privilege, alignment, or availability. An instruction reference and the handbook for the intended processor are the authority when writing a bootstrap, driver, or diagnostic.

A conceptual addressing example

MOV  (R2)+, -(SP)     ; copy one word, then advance R2 and push it
MOVB (R3)+, R0        ; copy a byte and sign-extend it through all of R0
CMP  6(PC), R1        ; compare R1 with a nearby word selected PC-relatively
BEQ  equal            ; branch if the Z condition code is set

For word autoincrement or autodecrement, the usual step is two bytes; byte operations generally step one byte, except that SP and PC retain word alignment behavior. MOVB into a register sign-extends into the high byte on the usual PDP-11 behavior, whereas many other byte operations affect only the low byte. Byte instructions make characters and packed data practical, but they are not a promise that arbitrary odd-address word accesses are safe or equally efficient on every implementation. Consult the processor handbook for the exact CPU being programmed.

N (negative), Z (zero), V (overflow), and C (carry) summarize an operation for branches such as BEQ, BNE, BPL, and unsigned comparisons. The condition codes are not merely a compiler detail: hand-written device code and assembly routines rely on them. Instructions such as EMT, TRAP, breakpoint operations, illegal-instruction conditions, and memory-management faults can transfer control through vectors. Device interrupts likewise arrive at a vector and priority level. Hardware saves the old PC and processor status on the stack, then loads a new PC and status from the vector; privileged operating-system code must establish a valid stack and vector table before enabling devices.

Address limits and memory management

A plain 16-bit virtual address names 64 KiB (32K 16-bit words) at one time. This is the central PDP-11 program constraint, even when a system contains more physical memory. Early systems, including the /20, expose that small address space directly. It is misleading to say every PDP-11 had virtual memory, or that every program could see all installed RAM. Memory-management hardware on later processors translated virtual addresses through registers describing address regions; it also provided protection and separate kernel/user mappings. A PDP-11/45-class machine has 18-bit physical addressing, for up to 256 KiB of physical memory, while the PDP-11/70 has 22-bit physical addressing, for up to 4 MiB. Exact MMU registers, physical address width, and supported options remain model-specific.

On machines with the relevant MMU, separate instruction and data (split I/D) spaces can give a process distinct 64 KiB instruction and 64 KiB data virtual spaces. This was valuable for Unix, whose program text and data otherwise competed in one small space. It is model- and operating-system-dependent: a /45-class system is well known for this facility, whereas a PDP-11/20 does not acquire it by belonging to the family. Even split I/D is not modern flat 32- or 64-bit virtual memory. Kernel mappings, swap strategies, overlays, and executable formats remain visible constraints in PDP-11 software design.

UNIBUS, Q-bus, and device reality

UNIBUS is the original PDP-11 shared system bus. It carries address, data, and control information and supports direct memory access (DMA), arbitration, and memory-mapped device registers. A disk controller or serial interface appears in the I/O page at reserved addresses rather than behind a modern plug-and-play discovery protocol. This regularity made drivers and third-party hardware possible, but it also means an incorrect board setting, terminator, grant continuity, or cable can prevent the whole system from working.

Q-bus, used by later LSI-11 and related systems, is a smaller multiplexed bus designed to reduce backplane and signal cost. It preserves much of the PDP-11 programming environment while changing electrical and mechanical details. Its physical address capability is not one family-wide number: the LSI-11/PDP-11/03 CPU exposes a 16-bit address space, including the I/O page, whereas Q18 describes bus/backplane capability; later applicable CPU/MMU combinations can use expanded physical addresses. Later 11/23 variants and 11/73-class systems must therefore be identified by their particular processor/MMU and whether the installed backplane is Q18 or Q22. A processor capable of 22-bit addressing cannot make a Q18 backplane, memory board, or controller perform 22-bit transfers. A Q-bus card is not a UNIBUS card, and compatibility should never be assumed from a controller’s initials alone. System documentation must match the bus, backplane, CPU, memory board, controller revision, and cabling.

Console, bootstrap, terminals, and storage

An early system may use a front-panel console with switches, lamps, examine/deposit controls, and start/halt functions. An operator could enter a small bootstrap loader by hand, load a paper-tape bootstrap, or use a ROM/console-assisted bootstrap on later equipment. The bootstrap initializes just enough state to ask a selected controller for the next block or record; that secondary loader brings in the operating-system image. “Boot from disk” is therefore a workflow involving the console, controller, media format, unit number, and sometimes DIP or jumper settings—not one universal key sequence.

Serial terminals were the normal human interface. A teletype could combine keyboard, printer, and paper-tape reader/punch at a slow data rate; video terminals later made interactive editing more comfortable. A current-loop or RS-232-like connection needs compatible electrical signaling, baud rate, character size, parity, stop bits, and flow control. Terminal escape behavior is software and terminal dependent. A serial prompt with garbled characters is often a configuration mismatch, not proof of a faulty CPU.

Example family	Medium or role	Careful interpretation
Paper tape	Bootstrap distribution, diagnostics, source exchange	Common early medium, but fragile and slow; reader/punch alignment and tape condition matter.
RK05 / RK	Removable cartridge disk	Often seen on smaller systems and early Unix installations; capacity and controller are not universal.
RL01 / RL02	Removable cartridge disk	Later popular disk family with model-specific controllers and media handling needs.
RP series	Larger disk packs/drives	Representative high-capacity PDP-11 storage, not a standard fitting in every cabinet.
TU series	Magnetic tape transports	Used for distribution, backup, and interchange; “TU” spans different drive and controller technologies.

These names identify families, not interchangeable media. A disk image must match its controller and operating-system driver; a tape reel may have a density, blocking convention, and filesystem expectation. Never treat a decades-old disk pack or tape as a casual test object. Make a read-oriented preservation copy using a known-good, aligned drive and appropriate interface where possible, record checksums and provenance, and retain the original unchanged.

Peripheral timing also shaped everyday operation. A terminal line could be much slower than memory, while a disk controller used DMA and interrupted when a transfer completed. A driver typically programs controller registers, starts an operation, then handles completion at its interrupt vector; it must synchronize with user processes and report errors such as an offline unit or bad media. This is why a PDP-11 system is best understood as CPU, bus, controller, cable, medium, and software together. Replacing one component with a modern interface can be useful, but it may hide the behavior a historical driver or diagnostic was written to observe.

Arithmetic options and operating systems

The base instruction set is distinct from optional or model-dependent arithmetic. EIS (Extended Instruction Set) supplied operations such as multiply, divide, and shifts on supported processors. FIS (Floating Instruction Set) and the more capable FPP (Floating-Point Processor) provided differing floating-point facilities. Software may probe, require, emulate, or avoid them; an instruction seen in a binary is not evidence that every PDP-11 executes it in hardware. This distinction matters when selecting a simulator CPU or installing a period program.

RT-11 is a single-user, real-time-oriented PDP-11 operating system widely used for laboratory and development work. RSX-11 is a family of real-time, multiuser systems, with variants and versions that should not be collapsed into one configuration. RSTS/E served time-sharing and educational environments, notably supporting many terminal users. Each system had its own drivers, command language, filesystem conventions, memory requirements, and supported processors. Saying “it ran on a PDP-11” is only the beginning of compatibility research.

Unix is another important PDP-11 resident, not the family’s default operating system. Bell Labs obtained a PDP-11 in 1970; First Edition Unix was documented in 1971 on a PDP-11/20. Later editions benefited from more capable PDP-11 configurations, including memory-management features. The architecture’s registers, byte operations, compact instruction encoding, and constrained address spaces shaped early C implementation choices and Unix kernels. That is a useful connection, not a claim that C was simply PDP-11 assembly or that all Unix behavior follows from one CPU. VAX, introduced later by DEC, is a distinct 32-bit architecture and product family; VAX Unix and BSD history should not be described as PDP-11 execution merely because they inherit ideas and software.

Preservation, simulation, and sources

Rack equipment contains real hazards. Disconnect mains before inspection; large power supplies can retain dangerous energy, and aged capacitors, wiring, fans, and line filters can fail. Do not defeat grounding, improvise mains repairs, or energize an unknown supply “just to see.” Backplane boards can be damaged by incorrect insertion, missing bus continuity, poor connectors, or ESD. Some later modules contain batteries whose leakage can corrode traces; inspect without assuming every system has one. Professional restoration help is appropriate for mains supplies, heavy drives, alignment, and unfamiliar high-voltage equipment.

Preserve documentation alongside hardware: module prints, engineering drawings, controller manuals, switch settings, serial numbers, and media labels often explain a nonstandard installation. Photograph before changing jumpers. Clean and reseat only with evidence and appropriate procedures; random board swaps can introduce faults. For software exploration, SIMH emulates several PDP-11 configurations and is invaluable for learning boot paths and operating systems without risking rare media. Obtain emulator software, firmware images, diagnostics, and operating-system distributions lawfully from their rights holders or repositories that state their authorization; preservation interest does not automatically grant redistribution rights.