February 26, 2025

Digital Circuit Design

Digital circuit design is built on two concepts: combinational logic (output depends only on current inputs) and sequential logic (output depends on current inputs and past state). Logic gates, flip-flops, and the building blocks assembled from them form the foundation of everything from a simple counter to a microprocessor. This covers the essential digital building blocks and the practical concerns that matter when you're actually building things.

Logic Gates and Boolean Algebra

The seven fundamental gates and their truth tables:

AND:  1 only if all inputs are 1       (A·B)
OR:   1 if any input is 1             (A+B)
NOT:  inverts the input               (Ā)
NAND: invert of AND — 0 only if all 1  NAND is functionally complete
NOR:  invert of OR — 1 only if all 0   NOR is also functionally complete
XOR:  1 if inputs differ              (A⊕B)
XNOR: 1 if inputs match               invert of XOR

"Functionally complete" means you can build any other logic function from NAND gates alone — or from NOR gates alone. This is why a NAND gate was historically the cheapest gate to manufacture and why old 7400-series designs often used all NANDs.

Flip-Flops — Storing State

A flip-flop stores one bit. It changes state only on a clock edge, which is what makes synchronous design tractable — everything updates at the same moment.

  • D flip-flop — captures input D on the rising clock edge. Most useful and most common. A register is just N D flip-flops sharing a clock.
  • T flip-flop — toggles when T=1 on the clock edge. Used in binary counters.
  • JK flip-flop — set (J=1,K=0), reset (J=0,K=1), toggle (J=1,K=1), hold (J=0,K=0). Flexible but needs careful handling to avoid the forbidden state.

Counters

Chain D or T flip-flops together and you get a counter. The output of each stage clocks the next.

4-bit binary counter: Q3 Q2 Q1 Q0
Counts: 0000, 0001, 0010, ... 1111, 0000 (16 states)

Modulo-10 (BCD) counter resets at 1010 (10):
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, ... (use NAND feedback to force reset)

The 74HC163 is a common synchronous 4-bit counter with preset, clear, and carry out. For longer counts, cascade multiple stages.

Shift Registers

Shift data in serial, out serial (SISO), or in serial, out parallel (SIPO), or the reverse. The 74HC595 is the classic serial-in, parallel-out shift register — send 8 bits over 3 wires (data, clock, latch) and get 8 parallel outputs. Widely used for expanding the number of digital outputs from a microcontroller with minimal pin count.

74HC595 — serial to 8 parallel outputs:
3 MCU pins (DATA, CLK, LATCH) → 8 output pins
Daisy-chainable for more outputs (16, 24, ...)

Combinational Logic Design

For complex combinational functions, use a Karnaugh map to minimise the expression before implementing:

Truth table → Boolean expression → K-map minimisation → simplified expression

Example: 3-input majority function (output 1 when ≥2 inputs are 1)
Full expression: ABC + ĀBC + AB̄C + ABĀ = AB + BC + AC (minimised)

In practice, FPGAs and PLDs handle this automatically — you write the logic in HDL and the synthesis tool minimises it. For small glue logic in a PCB design, use a single 74-series or 4000-series IC.

PLDs — Programmable Logic

  • GAL/PAL — small, cheap, one-time or reprogrammable. Used as glue logic to replace several small 74-series chips. GAL16V8 and GAL22V10 are common parts.
  • CPLD — larger, retains configuration without power. Altera/Intel MAX series, Lattice CPLD. Good for bus interface logic, state machines.
  • FPGA — very large, loses configuration on power-off (most store it in external SPI Flash). Xilinx, Altera, Lattice. Used when you need a lot of custom logic or high-speed digital processing. The iCE40 series from Lattice has free open-source toolchains (yosys + nextpnr), making it accessible for hobby use.

Timing and Metastability

Synchronous design only works if setup and hold times are met — the data must be stable before the clock edge arrives (setup time) and remain stable briefly after (hold time). Violate either and the flip-flop output is unpredictable. This becomes critical when crossing between clock domains (data generated in one clock domain, read in another).

The standard fix for clock-domain crossing: a two-stage synchroniser — two flip-flops in series, both clocked by the destination clock. This doesn't eliminate metastability but reduces the probability to negligible levels for slow signals. For fast data buses crossing domains, FIFOs with handshaking are used instead.

Signal Integrity at Speed

Above ~50MHz, traces on a PCB stop being "just wires" and start behaving as transmission lines. Reflections appear when source and load impedances don't match the trace impedance:

Trace impedance (microstrip, empirical approximation):
Z₀ ≈ 87/√(ε_r + 1.41) × ln(5.98h / (0.8w + t))

Where h = dielectric thickness, w = trace width, t = trace thickness, ε_r = dielectric constant

Standard FR4 PCB: ε_r ≈ 4.5
50Ω trace: typically 2.75mm wide on standard 1.6mm FR4 with 1oz copper

For high-speed signals, add series termination resistors (25–33Ω in series with the driver), keep traces short, and use solid ground planes.