Digital Circuit Design

Digital circuit design is built on two concepts: combinational logic (output depends only on current inputs) and sequential logic (output depends on current inputs and past state). Logic gates, flip-flops, and registers assembled from them form the foundation of everything from a simple counter to a microprocessor. Understanding these building blocks, plus the practical concerns of timing, signal integrity, and power, is what separates designs that work from designs that almost work.

Logic Families

Family	Supply	Speed	Power (static)	Output drive	Notes
74HC (High-Speed CMOS)	2–6V	Fast	Negligible	4–25mA	The default for 5V and 3.3V logic. Fast, low power.
74HCT	5V	Fast	Negligible	4–25mA	CMOS speed, TTL-compatible inputs (Vih=2.0V). Use for 5V TTL-interface compatibility.
74LVC	1.65–3.6V	Very fast	Negligible	24mA	3.3V logic. 5V-tolerant inputs on most. Good for 3.3V MCU to 5V legacy interface.
74AHC	2–5.5V	Very fast	Negligible	8–25mA	Advanced HC — faster edges, use with care near EMC limits
CMOS 4000-series	3–18V	Slow	Negligible	~1mA	Wide supply range. Old, slow. Still useful in high-voltage or wide-supply designs.
TTL (7400)	5V	Moderate	High (quiescent)	16–48mA	Classic. Now obsolete for new designs — replaced by HC/LVC.

Logic Gates and Boolean Algebra

AND:  output HIGH only if all inputs HIGH        Z = A · B
OR:   output HIGH if any input HIGH              Z = A + B
NOT:  inverts input                              Z = Ā
NAND: invert of AND                              Z = A·B̄  — functionally complete
NOR:  invert of OR                               Z = A+B̄  — also functionally complete
XOR:  HIGH if inputs differ                      Z = A⊕B
XNOR: HIGH if inputs match                       Z = A⊕B̄

"Functionally complete" = any logic function can be built from NAND alone
(or NOR alone) — which is why the 7400 NAND gate was historically so prevalent.

De Morgan's Laws

Ā·B̄ = (A+B)̄   → NAND of inputs = NOR of inverted inputs
Ā+B̄ = (A·B)̄   → NOR of inputs  = NAND of inverted inputs

Practical use: converting between gate types when you have only NAND or only NOR gates available.

Flip-Flops

Type	Inputs	Behaviour at clock edge	Common use
D (Data) flip-flop	D, CLK	Q follows D on rising edge	Registers, pipeline stages, most synchronous design
T (Toggle) flip-flop	T, CLK	Q toggles if T=1, holds if T=0	Binary counters
JK flip-flop	J, K, CLK	Set(J=1,K=0), Reset(J=0,K=1), Toggle(J=K=1), Hold(J=K=0)	Older designs; D flip-flop usually preferred now
SR latch (not clocked)	S, R	Set or Reset asynchronously; forbidden state S=R=1	Glitch-free switch debouncing

Counters

4-bit binary ripple counter (T flip-flops):
  Q0 toggles every cycle
  Q1 toggles every 2 cycles
  Q2 toggles every 4 cycles
  Q3 toggles every 8 cycles

Output: 0000→0001→0010→...→1111→0000 (16 states, period=16 clocks)

Modulo-N counter (e.g., divide-by-10 for BCD):
  74HC163 synchronous 4-bit counter:
  - Load (preset) terminal for modulo-N operation
  - NAND decode state 1001 (9), feed to CLR or LOAD → resets to 0 next cycle
  - Creates a ÷10 counter (0–9 sequence)

Cascading for longer counts:
  Carry-out of one 74HC163 → enable of next
  Two cascaded: 8-bit counter (0–255)

Shift Registers

74HC595 — Serial-In, Parallel-Out (SIPO):
  3 MCU pins → 8 parallel output pins

Send 8 bits: pulse CLK 8 times while setting DATA for each bit
Latch: pulse RCLK once — all 8 outputs update simultaneously
Daisy chain: QH' → next chip's SER for 16, 24, 32-bit expansion

74HC165 — Parallel-In, Serial-Out (PISO):
  8 parallel inputs → 3 MCU pins
  Use for reading many digital inputs with minimal pin count

State Machines

A finite state machine (FSM) is the standard design pattern for sequential logic with multiple states:

Moore machine: outputs depend only on current state
Mealy machine: outputs depend on current state AND inputs (faster response, fewer states)

Design procedure:
  1. Identify all states (draw state diagram)
  2. Assign binary codes to each state
  3. Derive next-state logic (truth table → K-map → gate equations)
  4. Derive output logic
  5. Implement with flip-flops + combinational logic

Example: vending machine controller (Moore)
  States: IDLE, COIN_IN, DISPENSE, CHANGE
  Inputs: coin_in, product_select, dispense_done
  Outputs: motor_on, change_motor_on

PLDs and FPGAs

Device	Capacity	Reprogrammable	Retains config?	Use case
GAL16V8 / GAL22V10	Small (16–22 inputs, 8–10 outputs)	Yes (EEPROM)	Yes	Glue logic replacement, bus interface, small state machines
CPLD (Lattice, Intel MAX)	Medium (hundreds of macrocells)	Yes (EEPROM/Flash)	Yes	Complex state machines, protocol converters, power sequencing
FPGA (iCE40, ECP5, Xilinx)	Large (thousands–millions of LUTs)	Yes (SRAM cells)	No (loads from SPI Flash at power-on)	DSP, custom protocols, neural inference, SoC designs

The iCE40 FPGA family from Lattice has a fully open-source toolchain (yosys + nextpnr + icestorm) — entry-level FPGA development with no proprietary tools. The iCEstick ($25) is a complete FPGA development board using this toolchain.

Timing and Metastability

Setup time (t_su): data must be stable before clock edge
Hold time (t_h):  data must remain stable after clock edge

Violate either → flip-flop enters metastable state → output undefined (not necessarily 0 or 1)
→ system errors, crashes, or data corruption

Clock domain crossing (CDC) — data generated in clock A, read in clock B:
  - If signals are slow (change << 1 cycle of either clock): two-stage synchroniser
  - If signals are fast (data bus): use asynchronous FIFO with Gray-coded read/write pointers

Reduces metastability probability by 2^N per stage (N ≈ 30 typical)

Signal Integrity at High Speed

Rule of thumb: signal starts behaving as transmission line when
  propagation delay > rise time / 6

FR4 propagation: ~170 ps/inch (velocity ~0.6c)
A 10-inch trace has 1.7ns propagation delay
With 1ns rise time: yes, this needs transmission line treatment

Signs of signal integrity problems on scope:
  - Overshoot and undershoot beyond supply rails
  - Ringing after edges
  - Double-clocking (false edges from reflections)

Fixes:
  - Series termination: 22–33Ω at driver output (absorbs reflections at source)
  - Parallel termination: resistor to Vcc/2 at receiver (absorbs at destination — costs DC current)
  - Keep signals short; avoid stubs; route cleanly over ground plane

References

• Wakerly — Digital Design Principles and Practices, 5th ed.
• Ciletti — Advanced Digital Design with the Verilog HDL
• Bogatin — Signal and Power Integrity Simplified
• nandland.com — FPGA and Verilog tutorials ↗
• HDLBits — Verilog practice problems ↗