Circuit Design in Practice
Designing a circuit well involves more than getting the schematic right. Simulation, PCB layout, thermal management, protection circuits, and systematic verification — these are the parts that determine whether a design that works in theory actually works on the bench, at temperature extremes, over component tolerance, and for years of operation in the field.
The Design Process
| Phase | What to do | Common mistakes |
|---|
| 1. Requirements | Write down: input range, output spec, power budget, temp range, cost target, regulatory requirements | Starting the schematic before requirements are clear — changes late are expensive |
| 2. Component selection | Select all major parts with 2× margin on current, voltage, and power ratings | Running components near their rated max — shortens life, increases failure rate |
| 3. Schematic | Draw with signal flow left→right, power top→bottom. Add all decoupling caps and test points. | Omitting decoupling from the schematic — it then gets forgotten in layout |
| 4. Simulation | Simulate switching supplies, precision analog paths, filter response, and loop stability | Skipping simulation, then discovering a stability issue on the assembled board |
| 5. Prototype | Breadboard or protoboard, verify function, find problems cheaply | Going straight to PCB — first-spin boards almost always have issues |
| 6. PCB layout | Apply layout rules, check DRC, review power planes and critical signal paths | Placing decoupling caps far from IC power pins; poor ground return paths |
| 7. Bring-up and test | Measure all supplies first, then functional tests, then parameter verification | Powering up fully assembled without checking supplies — burning everything |
Simulation Tools
| Tool | Cost | Best for | Notes |
|---|
| LTspice | Free | Analog, switching supplies, transient and AC analysis | The standard. Best free SPICE. Massive model library from Analog Devices + community. Download from analog.com |
| Falstad Circuit Simulator | Free (browser) | Quick sanity checks, teaching, visualisation | No install required. Interactive. Limited to simpler circuits but excellent for learning. |
| KiCad Simulator (ngspice) | Free | Simulating while drawing the schematic | SPICE built into KiCad 6+. Convenient for quick checks on your actual design. |
| Qucs-S | Free | RF, S-parameter, harmonic balance | Good for RF design where LTspice falls short |
| Cadence / Spectre | Commercial (expensive) | IC design, precise MOSFET models | Industry standard for custom IC. Not needed for board-level design. |
| Altium (schematic sim) | Commercial | PCB + simulation in one environment | Used in professional environments where the PCB tool is already Altium |
Schematic Best Practices
Signal flow: left to right
Power: top to bottom, VCC at top, GND at bottom — consistently
Labels: use net names ("ADC_IN", "MOTOR_PWM") not "net001"
References: R1, C1, U1 + value on schematic — not only in BOM
Test points: add TP1, TP2 markers — they become test pads in layout
Decoupling: add 100nF caps on every IC power pin in the schematic
→ forces you to actually place them in layout
Notes: add critical specs (V_ref tolerance, max Iout) as text notes
PCB Layout Rules
Ground Plane
A solid copper fill on one layer as a ground plane provides a low-impedance return path for every signal, reduces radiation, and makes decoupling capacitors actually work. Split planes (analog/digital ground) are sometimes recommended but often cause more problems than they solve — a single solid ground with careful component placement is usually better for mixed-signal boards.
Decoupling Capacitors
Rule: 100nF ceramic within 2mm of each IC VCC pin
Also: 10µF electrolytic per supply rail section (bulk decoupling)
Why placement matters:
Inductance of a via is ≈ 1nH/mm length
A cap 10mm from the IC pin has ≈ 10nH in series
At 100MHz: X_L = 2π × 10⁸ × 10⁻⁸ = 6.28Ω ← cap is nearly useless
Best practice:
Cap → via → via → IC power pin (shortest path)
Via-in-pad (cap pad has via directly through it) — best of all
Trace Current Capacity
1oz copper (35µm):
1mm wide → ~1A with ~10°C rise
2mm wide → ~2A
3mm wide → ~3A
For high currents:
V_drop = I × R_trace = I × (ρ_Cu × L / A)
ρ_Cu ≈ 1.72×10⁻⁸ Ω·m
Example: 2A through 100mm of 1mm-wide 1oz trace (1oz = 35µm thick):
A = 0.001m × 35×10⁻⁶m = 3.5×10⁻⁸ m²
R = 1.72×10⁻⁸ × 0.1 / 3.5×10⁻⁸ = 49.1mΩ
V_drop = 2A × 0.049Ω = 98mV — significant for low-voltage supplies
Controlled Impedance and High-Speed Signals
Above ~50MHz, PCB traces behave as transmission lines.
Characteristic impedance (microstrip approximation, FR4):
Z₀ ≈ (87 / √(ε_r + 1.41)) × ln(5.98h / (0.8w + t))
ε_r ≈ 4.5 for standard FR4
h = dielectric thickness (typically 0.25–0.8mm for outer layers on 4-layer board)
w = trace width, t = trace thickness (1oz ≈ 35µm)
Standard 50Ω microstrip: typically 2.75mm wide on 1.6mm FR4 outer layer
Rules for high-speed signals (USB, Ethernet, clock, LVDS):
- Match impedance to driver output impedance and cable
- Add series termination (25–33Ω) near driver for unterminated lines
- Route differential pairs with equal length (skew < 10ps/10mil typical)
- Keep pairs together — separation < 3× trace width
- Avoid vias in differential pairs when possible (each via = 0.3nH inductance)
Thermal Management
Every power-dissipating component has a thermal resistance chain:
Junction → Case → Heatsink → Ambient
T_junction = T_ambient + P × (θ_JC + θ_CS + θ_SA)
θ_JC — junction to case (datasheet)
θ_CS — case to heatsink (thermal compound; ~0.5–1°C/W with paste)
θ_SA — heatsink to ambient (heatsink datasheet)
Limit: T_junction < T_j_max − 20°C margin
Example: 7805 TO-220, P = 3.5W, T_amb = 40°C
θ_JC = 5°C/W
T_j (no heatsink, θ_JA=65°C/W): 40 + 3.5×65 = 267°C → fails (max 125°C)
Required total thermal resistance:
θ_total ≤ (125 − 40°C − 20°C margin) / 3.5W = 18.6°C/W
θ_JC = 5°C/W, θ_CS ≈ 0.5°C/W
Required θ_SA ≤ 18.6 − 5 − 0.5 = 13.1°C/W
→ Heatsink rated ≤ 13°C/W will keep the junction safe
Common Protection Circuits
| Protection | Circuit / component | Purpose |
|---|
| Overcurrent (load side) | Polyfuse, series fuse, current-limiting regulator | Prevent excess current damaging load or wiring |
| Reverse polarity | Series diode or P-MOSFET gate trick | Prevent reversed battery/connector destroying the circuit |
| Overvoltage (input) | TVS diode + fuse, crowbar (Zener + SCR) | Protect circuit from voltage spikes and surges |
| ESD (I/O pins) | TVS array, BAV99 (dual diode), steering diodes to rails | Protect IC inputs from static discharge |
| Inductive kickback | Flyback diode across any inductive load | Prevent transistor destruction when switching off inductive loads |
| Short circuit (supply) | Fuse, PTC resettable fuse (polyfuse) | Protect supply and wiring from dead shorts |
Board Bring-Up Sequence
- Inspect board under magnification — check for solder bridges, missing components, wrong polarities
- Check for short circuits before power: measure resistance between each supply rail and GND (unpowered)
- Power through a current-limited bench supply, set limit to expected idle current × 2
- Verify all supply voltages at their test points
- Check decoupling — probe each VCC rail with a scope (AC coupled, 20MHz limit) looking for noise
- Functional tests from simplest (GPIO toggling) to complex (full system)
- Verify worst-case parameters — max temperature, min supply voltage, max load current
References
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