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<h1>Digital Circuit Design</h1>
<p>Digital circuit design is built on two concepts: combinational logic (output depends only on current inputs) and sequential logic (output depends on current inputs and past state). Logic gates, flip-flops, and registers assembled from them form the foundation of everything from a simple counter to a microprocessor. Understanding these building blocks, plus the practical concerns of timing, signal integrity, and power, is what separates designs that work from designs that almost work.</p>

<h2>Logic Families</h2>

<table>
  <thead><tr><th>Family</th><th>Supply</th><th>Speed</th><th>Power (static)</th><th>Output drive</th><th>Notes</th></tr></thead>
  <tbody>
    <tr><td>74HC (High-Speed CMOS)</td><td>2–6V</td><td>Fast</td><td>Negligible</td><td>4–25mA</td><td>The default for 5V and 3.3V logic. Fast, low power.</td></tr>
    <tr><td>74HCT</td><td>5V</td><td>Fast</td><td>Negligible</td><td>4–25mA</td><td>CMOS speed, TTL-compatible inputs (Vih=2.0V). Use for 5V TTL-interface compatibility.</td></tr>
    <tr><td>74LVC</td><td>1.65–3.6V</td><td>Very fast</td><td>Negligible</td><td>24mA</td><td>3.3V logic. 5V-tolerant inputs on most. Good for 3.3V MCU to 5V legacy interface.</td></tr>
    <tr><td>74AHC</td><td>2–5.5V</td><td>Very fast</td><td>Negligible</td><td>8–25mA</td><td>Advanced HC — faster edges, use with care near EMC limits</td></tr>
    <tr><td>CMOS 4000-series</td><td>3–18V</td><td>Slow</td><td>Negligible</td><td>~1mA</td><td>Wide supply range. Old, slow. Still useful in high-voltage or wide-supply designs.</td></tr>
    <tr><td>TTL (7400)</td><td>5V</td><td>Moderate</td><td>High (quiescent)</td><td>16–48mA</td><td>Classic. Now obsolete for new designs — replaced by HC/LVC.</td></tr>
  </tbody>
</table>

<h2>Logic Gates and Boolean Algebra</h2>
<pre>
AND:  output HIGH only if all inputs HIGH        Z = A · B
OR:   output HIGH if any input HIGH              Z = A + B
NOT:  inverts input                              Z = Ā
NAND: invert of AND                              Z = A·B̄  — functionally complete
NOR:  invert of OR                               Z = A+B̄  — also functionally complete
XOR:  HIGH if inputs differ                      Z = A⊕B
XNOR: HIGH if inputs match                       Z = A⊕B̄

"Functionally complete" = any logic function can be built from NAND alone
(or NOR alone) — which is why the 7400 NAND gate was historically so prevalent.
</pre>

<h3>De Morgan's Laws</h3>
<pre>
Ā·B̄ = (A+B)̄   → NAND of inputs = NOR of inverted inputs
Ā+B̄ = (A·B)̄   → NOR of inputs  = NAND of inverted inputs

Practical use: converting between gate types when you have only NAND or only NOR gates available.
</pre>

<h2>Flip-Flops</h2>

<table>
  <thead><tr><th>Type</th><th>Inputs</th><th>Behaviour at clock edge</th><th>Common use</th></tr></thead>
  <tbody>
    <tr><td>D (Data) flip-flop</td><td>D, CLK</td><td>Q follows D on rising edge</td><td>Registers, pipeline stages, most synchronous design</td></tr>
    <tr><td>T (Toggle) flip-flop</td><td>T, CLK</td><td>Q toggles if T=1, holds if T=0</td><td>Binary counters</td></tr>
    <tr><td>JK flip-flop</td><td>J, K, CLK</td><td>Set(J=1,K=0), Reset(J=0,K=1), Toggle(J=K=1), Hold(J=K=0)</td><td>Older designs; D flip-flop usually preferred now</td></tr>
    <tr><td>SR latch (not clocked)</td><td>S, R</td><td>Set or Reset asynchronously; forbidden state S=R=1</td><td>Glitch-free switch debouncing</td></tr>
  </tbody>
</table>

<h2>Counters</h2>
<pre>
4-bit binary ripple counter (T flip-flops):
  Q0 toggles every cycle
  Q1 toggles every 2 cycles
  Q2 toggles every 4 cycles
  Q3 toggles every 8 cycles

Output: 0000→0001→0010→...→1111→0000 (16 states, period=16 clocks)

Modulo-N counter (e.g., divide-by-10 for BCD):
  74HC163 synchronous 4-bit counter:
  - Load (preset) terminal for modulo-N operation
  - NAND decode state 1001 (9), feed to CLR or LOAD → resets to 0 next cycle
  - Creates a ÷10 counter (0–9 sequence)

Cascading for longer counts:
  Carry-out of one 74HC163 → enable of next
  Two cascaded: 8-bit counter (0–255)
</pre>

<h2>Shift Registers</h2>
<pre>
74HC595 — Serial-In, Parallel-Out (SIPO):
  3 MCU pins → 8 parallel output pins
  
  MCU:  DATA ──────→ SER  (serial data in)
  MCU:  CLK  ──────→ SRCLK (shift clock)
  MCU:  LATCH ─────→ RCLK  (register clock / latch)
               QA..QH (8 parallel outputs)
               QH' (serial cascade output → next '595 SER pin)

Send 8 bits: pulse CLK 8 times while setting DATA for each bit
Latch: pulse RCLK once — all 8 outputs update simultaneously
Daisy chain: QH' → next chip's SER for 16, 24, 32-bit expansion

74HC165 — Parallel-In, Serial-Out (PISO):
  8 parallel inputs → 3 MCU pins
  Use for reading many digital inputs with minimal pin count
</pre>

<h2>State Machines</h2>
<p>A finite state machine (FSM) is the standard design pattern for sequential logic with multiple states:</p>
<pre>
Moore machine: outputs depend only on current state
Mealy machine: outputs depend on current state AND inputs (faster response, fewer states)

Design procedure:
  1. Identify all states (draw state diagram)
  2. Assign binary codes to each state
  3. Derive next-state logic (truth table → K-map → gate equations)
  4. Derive output logic
  5. Implement with flip-flops + combinational logic

Example: vending machine controller (Moore)
  States: IDLE, COIN_IN, DISPENSE, CHANGE
  Inputs: coin_in, product_select, dispense_done
  Outputs: motor_on, change_motor_on
</pre>

<h2>PLDs and FPGAs</h2>

<table>
  <thead><tr><th>Device</th><th>Capacity</th><th>Reprogrammable</th><th>Retains config?</th><th>Use case</th></tr></thead>
  <tbody>
    <tr><td>GAL16V8 / GAL22V10</td><td>Small (16–22 inputs, 8–10 outputs)</td><td>Yes (EEPROM)</td><td>Yes</td><td>Glue logic replacement, bus interface, small state machines</td></tr>
    <tr><td>CPLD (Lattice, Intel MAX)</td><td>Medium (hundreds of macrocells)</td><td>Yes (EEPROM/Flash)</td><td>Yes</td><td>Complex state machines, protocol converters, power sequencing</td></tr>
    <tr><td>FPGA (iCE40, ECP5, Xilinx)</td><td>Large (thousands–millions of LUTs)</td><td>Yes (SRAM cells)</td><td>No (loads from SPI Flash at power-on)</td><td>DSP, custom protocols, neural inference, SoC designs</td></tr>
  </tbody>
</table>

<p>The iCE40 FPGA family from Lattice has a fully open-source toolchain (yosys + nextpnr + icestorm) — entry-level FPGA development with no proprietary tools. The iCEstick ($25) is a complete FPGA development board using this toolchain.</p>

<h2>Timing and Metastability</h2>
<pre>
Setup time (t_su): data must be stable before clock edge
Hold time (t_h):  data must remain stable after clock edge

Violate either → flip-flop enters metastable state → output undefined (not necessarily 0 or 1)
→ system errors, crashes, or data corruption

Clock domain crossing (CDC) — data generated in clock A, read in clock B:
  - If signals are slow (change << 1 cycle of either clock): two-stage synchroniser
  - If signals are fast (data bus): use asynchronous FIFO with Gray-coded read/write pointers

Two-stage synchroniser for slow signals:
        clk_A domain       clk_B domain
  data ──[D-FF]──[D-FF]──── synced_data
               (clocked by clk_B both stages)
Reduces metastability probability by 2^N per stage (N ≈ 30 typical)
</pre>

<h2>Signal Integrity at High Speed</h2>
<pre>
Rule of thumb: signal starts behaving as transmission line when
  propagation delay > rise time / 6

FR4 propagation: ~170 ps/inch (velocity ~0.6c)
A 10-inch trace has 1.7ns propagation delay
With 1ns rise time: yes, this needs transmission line treatment

Signs of signal integrity problems on scope:
  - Overshoot and undershoot beyond supply rails
  - Ringing after edges
  - Double-clocking (false edges from reflections)

Fixes:
  - Series termination: 22–33Ω at driver output (absorbs reflections at source)
  - Parallel termination: resistor to Vcc/2 at receiver (absorbs at destination — costs DC current)
  - Keep signals short; avoid stubs; route cleanly over ground plane
</pre>

<h2>References</h2>
<ul>
  <li>Wakerly — <em>Digital Design Principles and Practices</em>, 5th ed.</li>
  <li>Ciletti — <em>Advanced Digital Design with the Verilog HDL</em></li>
  <li>Bogatin — <em>Signal and Power Integrity Simplified</em></li>
  <li><a href="https://www.nandland.com/" target="_blank" rel="noopener">nandland.com — FPGA and Verilog tutorials ↗</a></li>
  <li><a href="https://hdlbits.01xz.net/wiki/Main_Page" target="_blank" rel="noopener">HDLBits — Verilog practice problems ↗</a></li>
</ul>
