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<h1>Circuit Design in Practice</h1>
<p>Designing a circuit well involves more than getting the schematic right. Simulation, PCB layout, thermal management, protection circuits, and systematic verification — these are the parts that determine whether a design that works in theory actually works on the bench, at temperature extremes, over component tolerance, and for years of operation in the field.</p>

<h2>The Design Process</h2>

<table>
  <thead><tr><th>Phase</th><th>What to do</th><th>Common mistakes</th></tr></thead>
  <tbody>
    <tr><td>1. Requirements</td><td>Write down: input range, output spec, power budget, temp range, cost target, regulatory requirements</td><td>Starting the schematic before requirements are clear — changes late are expensive</td></tr>
    <tr><td>2. Component selection</td><td>Select all major parts with 2× margin on current, voltage, and power ratings</td><td>Running components near their rated max — shortens life, increases failure rate</td></tr>
    <tr><td>3. Schematic</td><td>Draw with signal flow left→right, power top→bottom. Add all decoupling caps and test points.</td><td>Omitting decoupling from the schematic — it then gets forgotten in layout</td></tr>
    <tr><td>4. Simulation</td><td>Simulate switching supplies, precision analog paths, filter response, and loop stability</td><td>Skipping simulation, then discovering a stability issue on the assembled board</td></tr>
    <tr><td>5. Prototype</td><td>Breadboard or protoboard, verify function, find problems cheaply</td><td>Going straight to PCB — first-spin boards almost always have issues</td></tr>
    <tr><td>6. PCB layout</td><td>Apply layout rules, check DRC, review power planes and critical signal paths</td><td>Placing decoupling caps far from IC power pins; poor ground return paths</td></tr>
    <tr><td>7. Bring-up and test</td><td>Measure all supplies first, then functional tests, then parameter verification</td><td>Powering up fully assembled without checking supplies — burning everything</td></tr>
  </tbody>
</table>

<h2>Simulation Tools</h2>

<table>
  <thead><tr><th>Tool</th><th>Cost</th><th>Best for</th><th>Notes</th></tr></thead>
  <tbody>
    <tr><td>LTspice</td><td>Free</td><td>Analog, switching supplies, transient and AC analysis</td><td>The standard. Best free SPICE. Massive model library from Analog Devices + community. Download from analog.com</td></tr>
    <tr><td>Falstad Circuit Simulator</td><td>Free (browser)</td><td>Quick sanity checks, teaching, visualisation</td><td>No install required. Interactive. Limited to simpler circuits but excellent for learning.</td></tr>
    <tr><td>KiCad Simulator (ngspice)</td><td>Free</td><td>Simulating while drawing the schematic</td><td>SPICE built into KiCad 6+. Convenient for quick checks on your actual design.</td></tr>
    <tr><td>Qucs-S</td><td>Free</td><td>RF, S-parameter, harmonic balance</td><td>Good for RF design where LTspice falls short</td></tr>
    <tr><td>Cadence / Spectre</td><td>Commercial (expensive)</td><td>IC design, precise MOSFET models</td><td>Industry standard for custom IC. Not needed for board-level design.</td></tr>
    <tr><td>Altium (schematic sim)</td><td>Commercial</td><td>PCB + simulation in one environment</td><td>Used in professional environments where the PCB tool is already Altium</td></tr>
  </tbody>
</table>

<h2>Schematic Best Practices</h2>
<pre>
Signal flow: left to right
Power:       top to bottom, VCC at top, GND at bottom — consistently
Labels:      use net names ("ADC_IN", "MOTOR_PWM") not "net001"
References:  R1, C1, U1 + value on schematic — not only in BOM
Test points: add TP1, TP2 markers — they become test pads in layout
Decoupling:  add 100nF caps on every IC power pin in the schematic
              → forces you to actually place them in layout
Notes:       add critical specs (V_ref tolerance, max Iout) as text notes
</pre>

<h2>PCB Layout Rules</h2>

<h3>Ground Plane</h3>
<p>A solid copper fill on one layer as a ground plane provides a low-impedance return path for every signal, reduces radiation, and makes decoupling capacitors actually work. Split planes (analog/digital ground) are sometimes recommended but often cause more problems than they solve — a single solid ground with careful component placement is usually better for mixed-signal boards.</p>

<h3>Decoupling Capacitors</h3>
<pre>
Rule: 100nF ceramic within 2mm of each IC VCC pin
Also: 10µF electrolytic per supply rail section (bulk decoupling)

Why placement matters:
  Inductance of a via is ≈ 1nH/mm length
  A cap 10mm from the IC pin has ≈ 10nH in series
  At 100MHz: X_L = 2π × 10⁸ × 10⁻⁸ = 6.28Ω  ← cap is nearly useless

Best practice:
  Cap → via → via → IC power pin (shortest path)
  Via-in-pad (cap pad has via directly through it) — best of all
</pre>

<h3>Trace Current Capacity</h3>
<pre>
1oz copper (35µm):
  1mm wide → ~1A with ~10°C rise
  2mm wide → ~2A
  3mm wide → ~3A

For high currents:
  V_drop = I × R_trace = I × (ρ_Cu × L / A)
  ρ_Cu ≈ 1.72×10⁻⁸ Ω·m
  
Example: 2A through 100mm of 1mm-wide 1oz trace (1oz = 35µm thick):
  A = 0.001m × 35×10⁻⁶m = 3.5×10⁻⁸ m²
  R = 1.72×10⁻⁸ × 0.1 / 3.5×10⁻⁸ = 49.1mΩ
  V_drop = 2A × 0.049Ω = 98mV — significant for low-voltage supplies
</pre>

<h3>Controlled Impedance and High-Speed Signals</h3>
<pre>
Above ~50MHz, PCB traces behave as transmission lines.
Characteristic impedance (microstrip approximation, FR4):

Z₀ ≈ (87 / √(ε_r + 1.41)) × ln(5.98h / (0.8w + t))

ε_r ≈ 4.5 for standard FR4
h = dielectric thickness (typically 0.25–0.8mm for outer layers on 4-layer board)
w = trace width, t = trace thickness (1oz ≈ 35µm)

Standard 50Ω microstrip: typically 2.75mm wide on 1.6mm FR4 outer layer

Rules for high-speed signals (USB, Ethernet, clock, LVDS):
  - Match impedance to driver output impedance and cable
  - Add series termination (25–33Ω) near driver for unterminated lines
  - Route differential pairs with equal length (skew < 10ps/10mil typical)
  - Keep pairs together — separation < 3× trace width
  - Avoid vias in differential pairs when possible (each via = 0.3nH inductance)
</pre>

<h2>Thermal Management</h2>
<pre>
Every power-dissipating component has a thermal resistance chain:
Junction → Case → Heatsink → Ambient

T_junction = T_ambient + P × (θ_JC + θ_CS + θ_SA)

θ_JC — junction to case (datasheet)
θ_CS — case to heatsink (thermal compound; ~0.5–1°C/W with paste)
θ_SA — heatsink to ambient (heatsink datasheet)

Limit: T_junction < T_j_max − 20°C margin

Example: 7805 TO-220, P = 3.5W, T_amb = 40°C
θ_JC = 5°C/W
T_j (no heatsink, θ_JA=65°C/W): 40 + 3.5×65 = 267°C → fails (max 125°C)

Required total thermal resistance:
θ_total ≤ (125 − 40°C − 20°C margin) / 3.5W = 18.6°C/W

θ_JC = 5°C/W, θ_CS ≈ 0.5°C/W
Required θ_SA ≤ 18.6 − 5 − 0.5 = 13.1°C/W
→ Heatsink rated ≤ 13°C/W will keep the junction safe
</pre>

<h2>Common Protection Circuits</h2>

<table>
  <thead><tr><th>Protection</th><th>Circuit / component</th><th>Purpose</th></tr></thead>
  <tbody>
    <tr><td>Overcurrent (load side)</td><td>Polyfuse, series fuse, current-limiting regulator</td><td>Prevent excess current damaging load or wiring</td></tr>
    <tr><td>Reverse polarity</td><td>Series diode or P-MOSFET gate trick</td><td>Prevent reversed battery/connector destroying the circuit</td></tr>
    <tr><td>Overvoltage (input)</td><td>TVS diode + fuse, crowbar (Zener + SCR)</td><td>Protect circuit from voltage spikes and surges</td></tr>
    <tr><td>ESD (I/O pins)</td><td>TVS array, BAV99 (dual diode), steering diodes to rails</td><td>Protect IC inputs from static discharge</td></tr>
    <tr><td>Inductive kickback</td><td>Flyback diode across any inductive load</td><td>Prevent transistor destruction when switching off inductive loads</td></tr>
    <tr><td>Short circuit (supply)</td><td>Fuse, PTC resettable fuse (polyfuse)</td><td>Protect supply and wiring from dead shorts</td></tr>
  </tbody>
</table>

<h2>Board Bring-Up Sequence</h2>
<ol>
  <li>Inspect board under magnification — check for solder bridges, missing components, wrong polarities</li>
  <li>Check for short circuits before power: measure resistance between each supply rail and GND (unpowered)</li>
  <li>Power through a current-limited bench supply, set limit to expected idle current × 2</li>
  <li>Verify all supply voltages at their test points</li>
  <li>Check decoupling — probe each VCC rail with a scope (AC coupled, 20MHz limit) looking for noise</li>
  <li>Functional tests from simplest (GPIO toggling) to complex (full system)</li>
  <li>Verify worst-case parameters — max temperature, min supply voltage, max load current</li>
</ol>

<h2>References</h2>
<ul>
  <li>Horowitz &amp; Hill — <em>The Art of Electronics</em>, 3rd ed.</li>
  <li>Ott — <em>Electromagnetic Compatibility Engineering</em></li>
  <li>Brooks — <em>PCB Currents: How They Flow, How They React</em></li>
  <li><a href="https://www.altium.com/documentation/altium-designer/pcb-design-guidelines" target="_blank" rel="noopener">Altium — PCB Design Guidelines ↗</a></li>
  <li><a href="https://www.analog.com/media/en/training-seminars/design-handbooks/Linear-Circuit-Design-Handbook/Linear_Circuit_Design_Handbook.pdf" target="_blank" rel="noopener">Analog Devices — Linear Circuit Design Handbook (PDF) ↗</a></li>
</ul>
